This invention relates to electron beam lithography and, more particularly, to marks utilized during lithography to achieve precise alignment of an electron beam with respect to a wafer on which high-resolution circuit patterns are to be defined by the beam in a multi-level direct-writing process.
It is well known that direct writing of a resist-coated semiconductor wafer with an electron beam can be employed to define high-resolution features for, for example, a very-large-scale-integrated (VLSI) circuit. In practice, circuit features are successively defined in the resist in a series of exposure steps. Following each exposure step, standard developing and processing steps such as etching, deposition, diffusion, etc., are carried out to form a prescribed pattern in the wafer. In this way, patterns are formed at successive so-called levels in the overall fabrication sequence. It is apparent that the patterns formed at these respective levels must be accurately aligned or registered with respect to each other.
In conventional electron beam lithography, it is known to form alignment marks on the wafer and to employ the marks for precisely registering the beam with respect to the wafer. In this way, the beam position is accurately initialized in preparation for a subsequent writing operation. During the registration step, the alignment marks are scanned by the beam in both the X and Y directions. Electrons backscattered from the scanned marks are detected and utilized to generate electrical signals. In turn, these signals serve as the basis for precisely positioning the beam with respect to the wafer, in a standard manner well known in the art.
Various publications describe the aforementioned alignment technique in more detail. These include the following articles: "EBES: A Practical Electron Lithographic System" by D. R. Herriott, R. J. Collier, D. S. Alles and J. W. Stafford, IEEE Transactions on Electron Devices, Vol. ED-22, No. 7, July 1975, pages 385-392; "Control System Design and Alignment Methods for Electron Lithography" by D. S. Alles, A. M. Johnson and R. L. Townsend, Journal of Vacuum Science Technology, Vol. 12, No. 6, November/December 1975, pages 1252-1256; "Experimental Scanning Electron-Beam Automatic Registration System" by A. D. Wilson et al, J. Vac. Sci. Techn., Vol. 12, No. 6, November/December 1975, pages 1266-1270; and "Issues in Fabricating Electron Devices With Submicrometer Dimensions" by R. C. Henderson et al, J. Vac. Sci. Tech., Vol. 16, No. 2, March/April 1979, pages 260-268.
Typical alignment marks heretofore utilized in electron beam lithography have comprised either trenches etched into the wafer or raised patterns made of a relatively high-atomic-number material formed on the surface of the wafer. In connection with the fabrication of some metal-oxide-semiconductor (MOS) devices, raised patterns made of tantalum have been suggested. But, in practice, applicants have found that alignment marks made of tantalum are not completely adequate for general use in fabricating VLSI MOS devices by direct-writing electron beam lithographic techniques.
Accordingly, efforts by workers in the field have been directed at trying to devise improved alignment marks for electron beam lithography. In particular, work has been directed at trying to find marks that are compatible with standard VLSI MOS fabrication techniques, that do not introduce contamination into the fabrication sequence, that are relatively inert and easily passivated, that are dimensionally stable and not degraded to any substantial extent during device processing steps such as thermal treatment and etching and, additionally, that provide a high backscattered-electron signal relative to that obtained from adjacent portions of the wafer surface.